
#define CPU_STAT(h, s)		((h)->mmu->cpu_stats->(s))
#define DMA_STAT(h, s)		((h)->mmu->dma_stats->(s))

struct cache_statistics {
	sim_size		hits;				// total cache hits
	sim_size		misses;				// total cache misses
	sim_size		writebacks;			// total cache lines written back
	sim_size		evictions;			// total cache lines evicted from cache
};

struct mmu_statistics {
	sim_size		stalls;				// Structural stalls triggered by the MMU
	sim_size		exceptions;			// Exceptions originating in the MMU
	sim_size		real_exceptions;	// Exceptions originating in the MMU that aren't clobbered

	sim_size		unmapped_reads;		// reads from unmapped virtual addresses
	sim_size		unmapped_writes;	// writes to unmapped virtual addresses

	sim_size		uncached_reads;		// reads from uncached memory regions
	sim_size		uncached_writes;	// writes to uncached memory regions

	sim_size		instruction_reads;	// total instruction reads
	sim_size		data_reads;			// total data reads (memory/device)
	sim_size		data_writes;		// total data writes (memory/device)

	sim_size		tlb_hits;			// Addresses found in TLB
	sim_size		tlb_misses;			// Addresses not found in TLB

	// The following include cache hits/misses:
	sim_size		ram_reads;			// Reads from RAM memory
	sim_size		ram_writes;			// Writes to RAM memory

	sim_cycle		ram_read_cycles;	// Cycles spent reading RAM memory
	sim_cycle		ram_write_cycles;	// Cycles spent writing RAM memory

	// NOTE: You can't write ROM so there are no statistics for that
	sim_size		rom_reads;			// Reads from ROM memory
	sim_size		rom_read_cycles;	// Cycles spent reading ROM memory

	sim_size		dev_reads;			// Reads from device memory
	sim_size		dev_writes;			// Writes to device memory

	sim_cycle		dev_read_cycles;	// Cycles spent reading device memory
	sim_cycle		dev_write_cycles;	// Cycles spent writing device memory
};

